Bottom-to-Top Links on the PCB (details)
PCB Traces from Bottom to Top < 6 cm
One 3D-Flow PE = 100K gates
See ASIC Design Verification (comparing system bit-vectors with gate-level bit-vectors)
See 3D-Flow System Monitoring (for troubleshooting and software repairs during run-time)
Top/Bottom I/O pins group (T/B) = 25 pins ([2 x (8+2)] + VCC, GND), Bit-0 Bottom is adjacent to Bit-0 Top, etc., for inserting jumpers between PCB pads when < 10 layers/board are required, thus not all 3DF chips are assembled
- less than 6 cm - Multiplexed 2:1
- less than 1.5 meters - Multiplexed (8+2):1
North, East, West, South pins group (NEWS) = 5 pins (2 LVDS transmitter, 2 LVDS receivers, 1 VCC/GND). LVDS operates at 2.5 mA into 100 ohm termination.
T/B group (25 pins) PE_15
NEWS group (5 pins) PE_15
.25 mm - 2.5 Volt 600 pins EBGA (4 x 4 cm)
.18 mm - 1.8 Volt 676 pins EBGA (2.7 x 2.7 cm)
Bottom-to-Top Links on the PCB (details)