PROGRAMMABLE LEVEL-0 (or 1) TRIGGER
Technology-Independent design (SOC-IP)
Technology-Independent & 3D-Flow architecture (High-Speed Real-time)
Benefits of a Technology Independent & 3D-Flow architecture design
Lower cost and higher performance of the novel approach
The evolution of IC design
Component of Technology Platform
Sustaining input data rate higher than time required to execute non-decomposable tasks
Executing non-decomposable algorithms (or pipeline stage) > 25 ns
Technology-Independent 3D-Flow ASIC (from CONCEPT to IMPLEMENTATION)
Overcoming the difficulties of “System On a Chip” VERIFICATION
Establishes the LINK between the user’s system algorithm and gate-level implementation
User’s high level of abstraction, no need to be bogged down into details of RTL
SW/HW Verification (1 PE)
Design VERIFICATION - COMPARE: “system Bit-Vectors” to “chip SW Bit-Vectors” to “HW Bit-Vectors”
Malfunction Monitoring During Real-Time Operation
Clock and Control Signals Distribution and Synchronization
Create & Simulate a 3D-Flow System (Particle Physics)
Description of the simulation of a system with 5956 PEs
FLEXIBILITY: different trigger algorithms can be loaded into the 3D-Flow system
Interface between detectors, triggers, and DAQ
LHCb Level-0 Trigger - Physical Layout
LHCb Level-0 Trigger - Logical Layout
Racks for the Level-0 Trigger
System Monitor for a 6144 channels 3D-Flow system
3D-Flow in HEP applications (3D-Flow crate performance)
Digital processing board. (Front view) ( 2048 digital inputs/outputs @ 40 MHz)
Digital processing board (rear view)
Level-0 FRONT-END signal synchronization, pipelining, FIFO, Trig word Formatting
FRONT-END circuit: VHDL coding & schematic of registering input data
FRONT-END circuit: VHDL coding and schematic of the selection of the variable delay
FRONT-END circuit: VHDL coding and schematic of the updating of the variable delays
FRONT-END circuit: VHDL coding and schematic of the formatting of the trigger word
FRONT-END circuit: VHDL coding and schematic of the pipeline buffer
3D-Flow FPGA front-end chip (detector signals & schematic of 4 channels)
Interface of FPGAs outputs to the DAQ through the serializer and fiber-optic transmitter
Summary of the signals propagation from the detector to the 3D-Flow trigger system on the digital processing board
3D-Flow System LVDS Links Neighboring Connection Scheme on the PCB
On board Bottom to Top Links and Logical Functionality of different 3D-Flow layers
Bottom-to-Top Links on the PCB (details)
3D-Flow System LVDS Links Neighboring Connection Scheme (off-board)
3D-Flow North, East, West, and South LVDS Links (on board, on crate, off-crate)
Crate-To-Crate Backplane LVDS Links (Hardware Implementation)
The 3D-Flow crate
Global Level-0 Trigger Decision Units
LHCb calorimeter Level-0 trigger layout and data rate
The 3D-Flow Architecture Optimized Features for Level-0 (or 1) Triggers
The 3D-Flow architecture simplifies the hardware implementation
Advantages of the 3D-Flow Architecture - Simplifies the hardware
Advantages of the 3D-Flow Architecture - Reduce the cost
Advantages of the 3D-Flow Architecture - Increased performance
Advantages of the 3D-Flow Architecture - Simplifies software tools design
Interrelation between entities in the Real-Time Design Process
3D-Flow Design Real-Time software tools
Breaking speed barriers in real-time applications
Email: Crosetto@Physics.rice.edu
Home Page: http://www.3D-Computing.com
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